5.03.00
Added PICE-52, PR2-52-HVC: Description of the hardware errors 0x59, 0x5A.
Added PICE-52, PR2-52-HVC; JEM-52, Mentor Graphics M8051EW (Micronas HVC): Generation of the warning when CodeMaster-52 tryes to write to the SFROM memory.
Changed PICE-52, PR2-52-HVC; JEM-52, Mentor Graphics M8051EW (Micronas HVC): The SFR description.
Improved PICE-52, PR2-52-HVC: The "Code memory" option default setting in the "Hardware configuration / Emulation MCU options" dialog is changed to the "Use emulator RAM as Code memory" setting.
Improved PICE-52, PR2-52-HVC; JEM-52, Mentor Graphics M8051EW (Micronas HVC): The contents of the error messages during FLASH memory programming.
Added JEM-52, JEM-HVC: Description of the hardware error 0x52.
Changed JEM-52, Mentor Graphics M8051EW (Micronas HVC): Writing to the Manufacturer NVRAM is prohibited now.
Improved JEM-52, Mentor Graphics M8051EW (Micronas HVC): 1-wire OCDI operation at 400 kHz TCK frequency.
Added: Progress bar when saving data files.
Fixed: Flash Erase and Debug Options commands are disabled if target is running.
5.02.02
Added: Support for Aeroflex UT69RH051 microcontroller.
5.02.01
Added JEM-52, Mentor Graphics M8051EW (Micronas HVC): Micronas HVC2480 Flash programming feature. Improved JEM-52, Mentor Graphics M8051EW (Micronas HVC): Single wire debug interface up to 500kHz of JTAG frequency.
5.02.00
Added PICE-52, PR2-52-HVC: Support of the Micronas HVC MCU on-chip Flash memory. Flash memory may be used now for code downloading and debugging.
Added PICE-52, PR2-52-HVC: The HVCA bondout chip peripherals freezing in the break mode. You may choose either to freeze HVCA peripherals or keep it running in the break mode.
Added PICE-52, PR2-52-HVC: Voltage measuring on the Vdd (+5V) and BVdd (+12V) pins of the HVCA bondout MCU. Older PODs need to reprogram Power monitor firmware and replace R8 resistor on the PR2-52-HVC POD board with 51 kOhm +/-1%.
5.01.04
Fixed PICE-52, PR2-52-HVC: PLL programming bug that caused the startup error.
Added PICE-52, PR2-52-HVC: Verification of the data exchange between Master and Emulation MCU.
5.01.03
Added PICE-52, PR2-52-HVC: Generation of the 0x59 and 0x5A error codes for timeout on some operations.
5.01.02
Improved PICE-52, PR2-52-HVC: The operation frequency increased up to 32MHz.
Fixed PICE-52, PR2-52-HVC: A bug in the I/O registers access procedure that caused an incorrect reading of the I/O registers data in the break mode.
Fixed PICE-52, PR2-52-HVC: A bug in the MCU reset procedure that skipped execution of the software (FHR) reset. So the Reset command under CodeMaster-52 IDE didn't reset the peripherals related to the FHR.
5.01.01
Added PICE-52, PR2-52-HVC: The Xdata memory Coverage support.
Fixed PICE-52, PR2-52-HVC: A critical bug in the JTAG access logic - caused an unexpected changing of the emulator's memory access address.
5.01.00
Added PICE-52, PR2-52-HVC: Code Coverage support.
Added PICE-52, PR2-52-HVC: The XDATA Shadow memory support.
Fixed PICE-52, PR2-52-HVC: Incorrect tracing timestamp for the Low-level steps.
5.00.42
Note JEM-52, JEM-HVC: EPM3064A device configuration must be updated via the Altera USB Blaster.
Added JEM-52, Mentor Graphics M8051EW (Micronas HVC): Support for single wire debug interface.
5.00.41
Note PICE-52, PR2-52-HVC: EPM3128A device configuration must be updated via the Altera USB Blaster.
Added PICE-52, PR2-52-HVC: Tracer start/stop triggers support.
Fixed PICE-52, PR2-52-HVC: Incorrect access to the SFRs of the emulation microcontroller.
Enhanced PICE-52, PR2-52-HVC: Setting and clearing of the breakpoint range becomes much faster.
Added: Support for Atmel AT89S54, AT89S58, AT89S64 microcontrollers.
Added: Working under control of IAR Embedded Workbench version 7.50+.
5.00.40
Fixed: Simulation of "MUL AB" instruction (CY, OV flags update).
Fixed: Timer0 peripheral window T0 states choice.
Fixed: Saving of configuration files when working from third-party IDEs.
Added PICE-52, PR2-52-HVC: Support for the following emulation features: Tracer, Complex Breakpoint Processor, Xdata breakpoints, Data breakpoints, Low-level step, Peripheral freezing, XRAM code debugging. EPM3128A device configuration must be updated via the Altera USB Blaster.
5.00.33
Fixed PICE-52: Working under control of IAR Embedded Workbench version 7.40+.
5.00.32
Fixed: Attempt to load code to invalid address space addresses caused an endless message loop.
Updated: Documentation.
5.00.31
Fixed: Simulation of "PUSH SP" instruction.
5.00.30
Added PICE-52, PR2-52-HVC: Preliminary release for the Micronas HVC family. The limited support for the HVC2480 microcontroller. The maximum emulation frequency is restricted up to 16 MHz.
Available features: File/Program downloading for debugging, Run, Stop, High-level step, Code breakpoints, access to the MCU memory and registers.
Unavailable features (not released in the current version): Tracer, Complex Breakpoint Processor, Xdata breakpoints, Data breakpoints, Low-level step, Peripheral freezing, XRAM code debugging, EEPROM and FLASH access.
Fixed PICE-52, PR2-52-HVC: Software bug in the startup sequence.
Fixed PICE-52, PR2-52-HVC: Bug in the Altera EPM3128 device configuration.
5.00.29
AddedPICE-52, PR2-52-HVC: Support for MCU Micronas HVC2480.
5.00.28
Changed: Debugging with JEM-52 works now for 30 days, after that it must be licensed.
5.00.27
Fixed JEM-52, Mentor Graphics M8051EW (Micronas HVC) DPTR1 content was destroyed if CODE or XDATA dump or disassembler window is open
Fixed JEM-52: Minor issues of operation when used with third-party IDEs.
5.00.26
FixedPICE-52, PR1-52-A5131: CodeMaster has a bug that prevented the operation of the PR1-52-A5131 POD.
5.00.25
Added: JEM-HVC support. For the Single-Wire DI is added test pattern generator only.
5.00.24
Updated PICE-52: Power monitor for PR1-52-ARX/RE2 pod.
5.00.23
Updated: Examples
5.00.22
Updated: CodeMaster-52 On-line Manual
5.00.21
Updated JEM-52, Mentor Graphics M8051EW (Micronas HVCA): Support driver for IAR Embedded Workbench v. 7.40+.
5.00.20
Added JEM-52, Mentor Graphics M8051EW (Micronas HVCA): Support for Forced Hardware Reset (FHR).
5.00.19
Fixed JEM-52: Working with software breakpoints when JEM is started from a third-party IDE
Added JEM-52: Support for id3 Semiconductors prototype
5.00.18
Added JEM-52, Mentor Graphics M8051EW, NXP/Philips LPC952: Support for combining complex breakpoints.
Added JEM-52, Mentor Graphics M8051EW: Start-up message concerning power management.
Fixed JEM-52, Mentor Graphics M8051EW: Writing to Extended Stack.
5.00.16
Fixed JEM-52: Atmel AT89LPxxx support
5.00.15
Added JEM-52: Support for NXP/Philips 89LPC952 chip
Changed: Key mappings for Step, Step Over, Low Level Step, Low Level Step Over, Make, Compile, Next Search and other commands
5.00.14
Added JEM-52, Mentor Graphics M8051EW: Support for Extended Stack (MG Extended Stack window).
Updated JEM-52, Mentor Graphics M8051EW: Program flow reconstruction algorithm for MG Hardware Tracer.
Added JEM-52, Mentor Graphics M8051EW: Support for Extended Operation SFR address in JEM-52 Hardware settings.
5.00.13
Updated JEM-52, Mentor Graphics M8051EW: Trace buffer reconstruction algorithm
5.00.12
Fixed: In certain cases, source text line numbers were not calculated correctly for IAR Systems UBROF files.
Fixed: Wrong linker options in banked model for IAR Systems projects
Updated JEM-52, Mentor Graphics M8051EW:
1. Tracer works now in 2 modes:
- when complex breakpoints are not used to control the tracer it is always enabled and CM-52 tries to restore the continuous trace history as far as it possible;
- when complex breakpoints are set to control the tracer then CM-52 displays the trace buffer "as is" - according to the data read directly from the trace memory.
2. The overflow indication (red icon in the leftmost trace column) is added now.
3. There is a possibility to power the target via pin 4 of the JTAG connector. This pin is powered by the programmable regulator controlled by the CM-52 Debug Options -> Power management dialog. To enable this feature in JEM-52 you should set the JP1 jumper on the TM2-52-FS-H20 board.
Fixed JEM-52, Mentor Graphics M8051EW: It is possible now to set hardware breakpoints while program is running.
Changed MCLINK Linker: CR/LF added to the last line of the HEX file.
5.00.11
Updated JEM-52: Enabled programming of AT89LP21x fuses
5.00.10
Added JEM-52: New POD TM2-52-FS-H20 supporting Micronas HVCA and NXP/Philips LPC952 chips.
Added JEM-52: Support for Mentor Graphics M8051EW hardware tracer.
5.00.09
Added JEM-52, HVCA: Support for extended core features: extended code addressing
Added JEM-52, HVCA: Peripheral device window for sequencer debugging
5.00.08
Added JEM-52, HVCA: Diagnostic of time-out of the Debug Commands Sequencer
Added JEM-52, HVCA: Changing of the On-Chip Debug Interface clock frequency
5.00.07
Added JEM-52, HVCA: Software breakpoints in RAM
Added JEM-52, HVCA: Error messages for "Invalid chip Id" and "JTAG Error"
5.00.06
Added JEM-52, HVCA: Loading program to RAM
Added JEM-52, HVCA: Hardware code breakpoints are implemented
5.00.05
Added: Preliminary release with Micronas HVCA device support. This release is for HVCA developers only. JEM-52 communicates with HAPA emulation board in 4-wire JTAG mode.
Fixed MCLINK Linker: Information on segment name/position and source file name/line added to diagnostic messages.
5.00.04
Updated JEM-52: Programming of AT89LP21x fuses is temporarily disabled
5.00.03
Added: Support for Atmel AT89LP214, AT89LP216 devices.
Added: Raisonance (R) C Compiler evaluation version included into the CodeMaster software package
5.00.02
Added: Support for Fuses/Lock Bits
5.00.01
Fixed: JEM-52 resident software Added: Fuses and lock bits warning dialogs
5.00.00
Beta Release