5.11.04 (Feb 28, 2013)
Fixed [PICE-52]: The script language variable TimeCounter had invalid value.
5.11.03 (Aug 3, 2012)
Changed: The MCA-51 assembler .include-files are updated.
5.11.02 (Jun 20, 2012)
Fixed [PICE-52, PR2-52-DS400/410/411]: User code loading at certain addresses could break the Slave monitor code.
Fixed: Error handling the memory settings for Kiel Software projects.
5.11.01 (May 15, 2012)
Fixed: Incorrect exit from the shell after the power monitor programming.
5.11.00 (May 11, 2012)
The FTDI USB driver has been updated to 2.08.24.
5.10.06 (Mar 20, 2012)
Fixed [MCA-51 Assembler]: Error handling long source lines.
Fixed [JEM-52, PICE-52]: Communication procedure via USB.
5.10.05 (Feb 15, 2012)
Fixed [JEM-52, Micronas HVC]: Under certain conditions the CodeMaster-52 could crash when displaying the contents of the MG trace buffer.
5.10.04 (Jan 18, 2012)
Updated: The procedure of establishing connection to the JTAG debugger is made more stable.
5.10.03 (Jan 16, 2012)
Updated: The CodeMaster-52 installation program now requires the administrator rights to run and the FTDI device drivers are installed correctly.
5.10.02
Updated: The FTDI USB device drivers.
Changed: When the "Enable flash caching" option is on, data in erased sectors are restored.
5.10.01
Added [JEM-52, Atmel AT89LPxxx family]: AT89LP428, AT89LP828, AT89LP6440 support.
5.10.00
Changed: The PICE-52 emulator will now work under the 64-bit Windows Vista and Windows 7. To learn about driver installation, click the "USB Driver Installation" icon.
Fixed: Loading a program containing long UNC paths to source files in the symbol information could cause the IDE error.
5.09.10
Fixed: Error on CodeMaster exit.
5.09.09
Added [PICE-52, PR2-52-ARX/ID2]: Support for Atmel AT89S54, AT89S58, AT89S64 microcontrollers.
5.09.08
Added: Integration with IAR Systems IAR Embedded Workbench version 7.6x.
5.09.07
Added [PICE-52, PR2-52-DS411]: Support for Maxim (Dallas) DS80C411 microcontroller.
5.09.06
Fixed: Errors when building the Raisonance S. A. package projects.
5.09.05
Fixed: Handling older versions of the IAR Systems UBROF files.
Fixed [PICE-52]: Banking breakpoint issues for AT89C51RE2 chip.
5.09.04
Fixed [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: Version 5.09.03 did not display the "Turn off and on the target board power..." warning message.
5.09.03
Fixed [PICE-52]: Changing certain hardware configuration settings could cause a hadrware error.
5.09.02
Fixed: Selecting the Simulator after the PICE-52 In-Circuit Emulator could cause error when displaying local menu in the Disassembler window.
5.09.01
Fixed: Selecting the Simulator after the PICE-52 In-Circuit Emulator could cause error when displaying local menu in the Source/Editor window.
Fixed [PICE-52, PR2-52-ARX]: MR2-52-06 Main Board 2 MB code banking memory support. Due to the bug in the FPGA configuration only 1 MB of the code memory was actually available.
Fixed [PICE-52]: Incorrect usage of the registers in the break mode in case of PSW set to non-zero register bank.
5.09.00
Added [PICE-52, PR2-52-HVC]: MG Extended Hardware Stack view for all MG emulated targets.
Changed [PICE-52, PR2-52-HVC]: HVC2480 chip is selected by default.
Fixed [PICE-52, PR2-52-HVC]: Tracer window refresh at run-time when trace start/stop triggers is defined.
Fixed [PICE-52, PR2-52-HVC]: Symbol list is now available for complex breakpoints on DATA/IDATA memory.
5.08.00
Updated: CodeMaster-52 On-line manual
Fixed [PICE-52, PR2-52-HVC, HVC2005A-B4]: States of the BPP triggers sometimes were traced with errors.
Fixed [JEM-52, Mentor Graphics M8051EW (Micronas HVC): HVC2280A memory map.
Fixed [JEM-52, Mentor Graphics M8051EW (Micronas HVC): Extended Stack window is excluded for HVC2280A, HVC2480A.
Improved [PICE-52, PR2-52-HVC, HVC2005A-B4]: Now the Tracer stores the BPP trigger states in the Tracer frames without any delay.
Changed [PICE-52, PR2-52-HVC, HVC2005A-B4]: Now PICE-52 does not restrict an access to the bits SR0[3] and SR0[6] in the Break mode.
5.07.00
Fixed [PICE-52, PR2-52-HVC, HVC2005A-B4]: Bugs in the Breakpoint Processor.
Added [PICE-52, PR2-52-HVC, HVC2005A-B4]: Support for the tracer External Inputs.
Added [PICE-52, PR2-52-HVC, HVC2005A-B4]: The target BVdd (12 V) voltage control. PICE-52 generates an error message when the target BVdd voltage is not supplied.
Changed [JEM-52, Mentor Graphics M8051EW (Micronas HVC), PICE-52, PR2-52-HVC]: The Erase Flash memory option is disabled for the HVC2280 target microcontroller.
Changed [PICE-52, PR2-52-HVC]: PICE-52 does not try to erase the emulation microcontroller Flash memory when the "Use emulator RAM as Code memory" hardware configuration option is selected.
5.06.00
Added [JEM-52, Mentor Graphics M8051EW (Micronas HVC), PICE-52, PR2-52-HVC]: Support for the Micronas HVC2280A microcontroller.
Fixed [PICE-52, PR2-52-HVC, HVC2005A-B4]: PICE-52 failed if the emulation MCU reset (FHR reset or WDT reset) occured while PICE-52 was executing the transition from Run mode to Break mode. To apply the update you should reprogram the EPM328A FPGA on the PR2-52-HVC board. Contact Phyton for details.
5.05.00
Added [PICE-52, PR2-52-HVC]: Support for the HVC2005A emulation microcontroller revision B4.
Fixed [PICE-52, PR2-52-HVC, HVC2005A-B4]: The Code breakpoint placed at Reset Vector (address 0) did not trigger after emulation MCU Reset.
5.04.08
Fixed: Handling of PDATA variables for IAR Systems UBROF files.
5.04.07
Changed [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: More precise JTAG frequency indication.
Added [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: 1-wire or 4-wire OCDI selection. Separate JTAG frequency settings for 1-wire and 4-wire OCDI.
Fixed: Handling of PDATA variables for IAR Systems UBROF files.
5.04.06
Changed [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: "Allow debugging in SLOW mode" flag default value has been changed to "OFF".
5.04.05
Fixed: Displaying the Global Debug/Display Options from the Watch window -> Setup dialog.
5.04.04
Updated: CodeMaster-52 On-line manual
5.04.03
Changed [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: SLEEP/IDLE mode workaround.
Updated: CodeMaster-52 On-Line Manual.
5.04.02
Fixed [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: FHR over RUN mode.
Fixed [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: CPU peripheral window view.
Added [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: SLOW mode support.
Changed [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: SLEEP/IDLE mode workaround.
Fixed [PICE-52, PR2-52-HVC]: The PICE-52 hardware read the SR0 register incorrectly when the MCU Slow mode was enabled.
Added [PICE-52, PR2-52-HVC, JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: Target MCU reset before flash programming
Added [PICE-52, PR2-52-HVC]: At the user attempt to reset the emulation MCU while it is in the IDLE or SLEEP modes CodeMaster prevents the reset execution and displays an appropriate message.
5.04.01
Fixed [PICE-52, PR2-52-ARX/S58RC]: The bug in the EXTRAM bit (AUXR.1) value reconstruction method. The EXTRAM bit reset value was incorrectly reconstructed by the emulator as "0" instead of "1".
Fixed [PICE-52, PR2-52-ARX/S58RC]: The bugs in the SST89C58RC.SFR, SST89C58RC.INC SFR description files.
Improved [PICE-52, PR2-52-DS450]: Reading of the P3.6, P3.7 latches when the "Use P3.6, P3.7 as: Write/Read Control Pins" option was selected caused the hardware error #0x24. Now the latches reading is skipped and always read as "1".
5.04.00
Added [PICE-52, PR2-52-ARX/S58RC]: New POD PR2-52-ARX/S58RC supports the SST 89C58RC chip emulation.
Added [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: SLEEP/IDLE mode workaround. Fixed [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: Incorrect R0 register reading.
Fixed [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: Single wire interface start-up sequence missing.
Changed [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: EO register default address set to 0x86
Fixed [PICE-52, PR2-52-HVC]: Incorrect XData access breakpoint settings.
Fixed [PICE-52, PR2-52-HVC]: Code memory reading bug in the break mode. While reading bytes with low byte addresses 0x68, 0x6A PICE-52 corrupted the read data.
5.03.00
Added [PICE-52, PR2-52-HVC]: Description of the hardware errors 0x59, 0x5A.
Added [PICE-52, PR2-52-HVC; JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: Generation of the warning when CodeMaster-52 tryes to write to the SFROM memory.
Changed [PICE-52, PR2-52-HVC; JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: The SFR description.
Improved [PICE-52, PR2-52-HVC]: The "Code memory" option default setting in the "Hardware configuration / Emulation MCU options" dialog is changed to the "Use emulator RAM as Code memory" setting.
Improved [PICE-52, PR2-52-HVC; JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: The contents of the error messages during FLASH memory programming.
Added [JEM-52, JEM-HVC]: Description of the hardware error 0x52.
Changed [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: Writing to the Manufacturer NVRAM is prohibited now.
Improved [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: 1-wire OCDI operation at 400 kHz TCK frequency.
Added: Progress bar when saving data files.
Fixed: Flash Erase and Debug Options commands are disabled if target is running.
5.02.02
Added: Support for Aeroflex UT69RH051 microcontroller.
5.02.01
Added [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: Micronas HVC2480 Flash programming feature. Improved [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: Single wire debug interface up to 500kHz of JTAG frequency.
5.02.00
Added [PICE-52, PR2-52-HVC]: Support of the Micronas HVC MCU on-chip Flash memory. Flash memory may be used now for code downloading and debugging.
Added [PICE-52, PR2-52-HVC]: The HVCA bondout chip peripherals freezing in the break mode. You may choose either to freeze HVCA peripherals or keep it running in the break mode.
Added [PICE-52, PR2-52-HVC]: Voltage measuring on the Vdd (+5V) and BVdd (+12V) pins of the HVCA bondout MCU. Older PODs need to reprogram Power monitor firmware and replace R8 resistor on the PR2-52-HVC POD board with 51 kOhm +/-1%.
5.01.04
Fixed [PICE-52, PR2-52-HVC]: PLL programming bug that caused the startup error.
Added [PICE-52, PR2-52-HVC]: Verification of the data exchange between Master and Emulation MCU.
5.01.03
Added [PICE-52, PR2-52-HVC]: Generation of the 0x59 and 0x5A error codes for timeout on some operations.
5.01.02
Improved [PICE-52, PR2-52-HVC]: The operation frequency increased up to 32MHz.
Fixed [PICE-52, PR2-52-HVC]: A bug in the I/O registers access procedure that caused an incorrect reading of the I/O registers data in the break mode.
Fixed [PICE-52, PR2-52-HVC]: A bug in the MCU reset procedure that skipped execution of the software (FHR) reset. So the Reset command under CodeMaster-52 IDE didn't reset the peripherals related to the FHR.
5.01.01
Added [PICE-52, PR2-52-HVC]: The Xdata memory Coverage support.
Fixed [PICE-52, PR2-52-HVC]: A critical bug in the JTAG access logic - caused an unexpected changing of the emulator's memory access address.
5.01.00
Added [PICE-52, PR2-52-HVC]: Code Coverage support.
Added [PICE-52, PR2-52-HVC]: The XDATA Shadow memory support.
Fixed [PICE-52, PR2-52-HVC]: Incorrect tracing timestamp for the Low-level steps.
5.00.42
Note [JEM-52, JEM-HVC]: EPM3064A device configuration must be updated via the Altera USB Blaster.
Added [JEM-52, Mentor Graphics M8051EW (Micronas HVC)]: Support for single wire debug interface.
5.00.41
Note [PICE-52, PR2-52-HVC]: EPM3128A device configuration must be updated via the Altera USB Blaster.
Added [PICE-52, PR2-52-HVC]: Tracer start/stop triggers support.
Fixed [PICE-52, PR2-52-HVC]: Incorrect access to the SFRs of the emulation microcontroller.
Enhanced [PICE-52, PR2-52-HVC]: Setting and clearing of the breakpoint range becomes much faster.
Added: Support for Atmel AT89S54, AT89S58, AT89S64 microcontrollers.
Added: Working under control of IAR Embedded Workbench version 7.50+.
5.00.40
Fixed: Simulation of "MUL AB" instruction (CY, OV flags update).
Fixed: Timer0 peripheral window T0 states choice.
Fixed: Saving of configuration files when working from third-party IDEs.
Added [PICE-52, PR2-52-HVC]: Support for the following emulation features: Tracer, Complex Breakpoint Processor, Xdata breakpoints, Data breakpoints, Low-level step, Peripheral freezing, XRAM code debugging. EPM3128A device configuration must be updated via the Altera USB Blaster.
5.00.33
Fixed [PICE-52]: Working under control of IAR Embedded Workbench version 7.40+.
5.00.32
Fixed: Attempt to load code to invalid address space addresses caused an endless message loop.
Updated: Documentation.
5.00.31
Fixed: Simulation of "PUSH SP" instruction.
5.00.30
Added [PICE-52, PR2-52-HVC]: Preliminary release for the Micronas HVC family. The limited support for the HVC2480 microcontroller. The maximum emulation frequency is restricted up to 16 MHz.
Available features: File/Program downloading for debugging, Run, Stop, High-level step, Code breakpoints, access to the MCU memory and registers.
Unavailable features (not released in the current version): Tracer, Complex Breakpoint Processor, Xdata breakpoints, Data breakpoints, Low-level step, Peripheral freezing, XRAM code debugging, EEPROM and FLASH access.
Fixed [PICE-52, PR2-52-HVC]: Software bug in the startup sequence.
Fixed [PICE-52, PR2-52-HVC]: Bug in the Altera EPM3128 device configuration.
5.00.29
Added[PICE-52, PR2-52-HVC]: Support for MCU Micronas HVC2480.
5.00.28
Changed: Debugging with JEM-52 works now for 30 days, after that it must be licensed.
5.00.27
Fixed [JEM-52, Mentor Graphics M8051EW (Micronas HVC)] DPTR1 content was destroyed if CODE or XDATA dump or disassembler window is open
Fixed [JEM-52]: Minor issues of operation when used with third-party IDEs.
5.00.26
Fixed[PICE-52, PR1-52-A5131]: CodeMaster has a bug that prevented the operation of the PR1-52-A5131 POD.
5.00.25
Added: JEM-HVC support. For the Single-Wire DI is added test pattern generator only.
5.00.24
Updated [PICE-52]: Power monitor for PR1-52-ARX/RE2 pod.
5.00.23
Updated: Examples
5.00.22
Updated: CodeMaster-52 On-line Manual
5.00.21
Updated [JEM-52, Mentor Graphics M8051EW (Micronas HVCA)]: Support driver for IAR Embedded Workbench v. 7.40+.
5.00.20
Added [JEM-52, Mentor Graphics M8051EW (Micronas HVCA)]: Support for Forced Hardware Reset (FHR).
5.00.19
Fixed [JEM-52]: Working with software breakpoints when JEM is started from a third-party IDE
Added [JEM-52]: Support for id3 Semiconductors prototype
5.00.18
Added [JEM-52, Mentor Graphics M8051EW, NXP/Philips LPC952]: Support for combining complex breakpoints.
Added [JEM-52, Mentor Graphics M8051EW]: Start-up message concerning power management.
Fixed [JEM-52, Mentor Graphics M8051EW]: Writing to Extended Stack.
5.00.16
Fixed [JEM-52]: Atmel AT89LPxxx support
5.00.15
Added [JEM-52]: Support for NXP/Philips 89LPC952 chip
Changed: Key mappings for Step, Step Over, Low Level Step, Low Level Step Over, Make, Compile, Next Search and other commands
5.00.14
Added [JEM-52, Mentor Graphics M8051EW]: Support for Extended Stack (MG Extended Stack window).
Updated [JEM-52, Mentor Graphics M8051EW]: Program flow reconstruction algorithm for MG Hardware Tracer.
Added [JEM-52, Mentor Graphics M8051EW]: Support for Extended Operation SFR address in JEM-52 Hardware settings.
5.00.13
Updated [JEM-52, Mentor Graphics M8051EW]: Trace buffer reconstruction algorithm
5.00.12
Fixed: In certain cases, source text line numbers were not calculated correctly for IAR Systems UBROF files.
Fixed: Wrong linker options in banked model for IAR Systems projects
Updated [JEM-52, Mentor Graphics M8051EW]:
1. Tracer works now in 2 modes:
- when complex breakpoints are not used to control the tracer it is always enabled and CM-52 tries to restore the continuous trace history as far as it possible;
- when complex breakpoints are set to control the tracer then CM-52 displays the trace buffer "as is" - according to the data read directly from the trace memory.
2. The overflow indication (red icon in the leftmost trace column) is added now.
3. There is a possibility to power the target via pin 4 of the JTAG connector. This pin is powered by the programmable regulator controlled by the CM-52 Debug Options -> Power management dialog. To enable this feature in JEM-52 you should set the JP1 jumper on the TM2-52-FS-H20 board.
Fixed [JEM-52, Mentor Graphics M8051EW]: It is possible now to set hardware breakpoints while program is running.
Changed [MCLINK Linker]: CR/LF added to the last line of the HEX file.
5.00.11
Updated [JEM-52]: Enabled programming of AT89LP21x fuses
5.00.10
Added [JEM-52]: New POD TM2-52-FS-H20 supporting Micronas HVCA and NXP/Philips LPC952 chips.
Added [JEM-52]: Support for Mentor Graphics M8051EW hardware tracer.
5.00.09
Added [JEM-52, HVCA]: Support for extended core features: extended code addressing
Added [JEM-52, HVCA]: Peripheral device window for sequencer debugging
5.00.08
Added [JEM-52, HVCA]: Diagnostic of time-out of the Debug Commands Sequencer
Added [JEM-52, HVCA]: Changing of the On-Chip Debug Interface clock frequency
5.00.07
Added [JEM-52, HVCA]: Software breakpoints in RAM
Added [JEM-52, HVCA]: Error messages for "Invalid chip Id" and "JTAG Error"
5.00.06
Added [JEM-52, HVCA]: Loading program to RAM
Added [JEM-52, HVCA]: Hardware code breakpoints are implemented
5.00.05
Added: Preliminary release with Micronas HVCA device support. This release is for HVCA developers only. JEM-52 communicates with HAPA emulation board in 4-wire JTAG mode.
Fixed [MCLINK Linker]: Information on segment name/position and source file name/line added to diagnostic messages.
5.00.04
Updated [JEM-52]: Programming of AT89LP21x fuses is temporarily disabled
5.00.03
Added: Support for Atmel AT89LP214, AT89LP216 devices.
Added: Raisonance (R) C Compiler evaluation version included into the CodeMaster software package
5.00.02
Added: Support for Fuses/Lock Bits
5.00.01
Fixed: JEM-52 resident software Added: Fuses and lock bits warning dialogs
5.00.00
Beta Release