Hardware characteristics of ChipProg-ISP

1.Has a standard 14 pin connector.

2.By default is supplied with a flat ribbon cable with dual headers - 10- and 14 pins.

3.Optionally can be supplied with several cable adapters for programming specific device families.

4.The programmer is built on the base of a very fast and productive 32-bit embedded microcontroller and a FPGA device.

5.Most timing-critical parts of the programming algorithms are implemented in the FPGA devices.

6.Implementation in the FPGA devices logical drivers enable outputting logical signals of any level (low, high, Pullup, Pulldown and external clock generator) to any pin of the programming connector.

7.The programmers's hardware features 10-bit digital-to-analog converters for accurate settings of the analog signals.

8.The programmers's hardware enables accurate programming of the rising and falling edges of the generated analog signals.

9.The programmers's hardware automatically adjusts the generated analog signals.

10.The generated analog signals for both the target supplying and programming can be outputted to any pins of the device being programmed.

11. The programmers's hardware protects itself and the target device against incorrect connection.

12. The target device pins are protected against the electrostatic discharge.

13. Can be started from the external signal.

14. Three status signals “Good”, “Busy”, “Error” are outputted to the programmer connector for driving ATE equipment.

15. The self-testing procedure can be executes at any time by request.